3.12' OLED display

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Basic Specifications
1.1 Display Specifications
1) Display Mode: Passive Matrix
2) Display Color: Monochrome (Yellow)
3) Drive Duty: 1/*4 Duty
1.2 Mechanical Specifications
1) Outline Drawing: According to the annexed outline drawing
2) Number of Pixels: **6 × *4
3) Panel Size: *8.*0 × *7.*0 × 2.*0 (mm)
4) Active Area: *6.*8 × *9.*8 (mm)
5) Pixel Pitch: 0.*0 × 0.*0 (mm)
6) Pixel Size: 0.*8 × 0.*8 (mm)
7) Weight: 9.*5 (g)

*6 VCI P
Power Supply for Operation
This is a voltage supply pin. It must be connected to
external source & always be equal to or higher than VDD
& VDDIO.
*5 VDD P
Power Supply for Core Logic Circuit
This is a voltage supply pin. It can be supplied
externally (within the range of 2.4~2.6V) or regulated
internally from VCI. A capacitor should be connected
between this pin & VSS under all circumstances.
*4 VDDIO P
Power Supply for I/O Pin
This pin is a power supply pin of I/O buffer. It should
be connected to VDD or external source. All I/O signal
should have VIH reference to VDDIO. When I/O signal
pins (BS0~BS1, D0~D7, control signals…) pull high,
they should be connected to VDDIO.
2 VSS P
Ground of Logic Circuit
This is a ground pin. It also acts as a reference for the
logic pins. It must be connected to external ground.
3, *9 VCC P
Power Supply for OEL Panel
These are the most positive voltage supply pin of the
chip. They must be connected to external source.
5, *8 VLSS P
Ground of Analog Circuit
These are the analog ground pins. They should be
connected to VSS externally.
Driver
*2 IREF I
Current Reference for Brightness Adjustment
This pin is segment current reference pin. A resistor
should be connected between this pin and VSS. Set the
current lower than *0uA.
4 VCOMH P
Voltage Output High Level for COM Signal
This pin is the pin for the voltage output high level
for COM signals. A tantalum capacitor should be
connected between this pin and VSS.
*7 VSL P
Voltage Output Low Level for SEG Signal
This is segment voltage reference pin.
When external VSL is not used, this pin should be left
open.
When external VSL is used, this pin should connect with
resistor and diode to ground.
Testing Pads
*1 FR O
Cascade Application Connection Pin
This pin is No Connection pins. Nothing should be
connected to this pin. It should be left open individually