الوصف

ValueRAM's 1G x **-bit (8GB) DDR*-
***0 CL*1 SDRAM (Synchronous DRAM) 2Rx8, memory
module, based on sixteen **2M x *-bit FBGA components. The
SPD is programmed to JEDEC standard latency DDR*****0
timing of *******1 at 1.5V. This ***-pin SODIMM uses gold
contact fingers. The electrical and mechanical specifications
are as follows:

• JEDEC standard 1.5V (1.**5V ~1.**5V) Power Supply
• VDDQ = 1.5V (1.**5V ~ 1.**5V)
• **0MHz fCK for ***0Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: *1, *0, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• *-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “**0” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A*2 or
MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : **0 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE *5°C,
3.9us at *5°C < TCASE < *5°C
• Asynchronous Reset
• PCB : Height 1.**0” (*0.*0mm), double sided component