الوصف

W***4G6JH*6 is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words × 4 banks × *6 bits. Using pipelined architecture and 0.**5 μm process technology,
W***4G6JH*6 delivers a data bandwidth of up to **6M bytes per second (*7).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W***4G6JH*6 is ideal for main memory in
high performance applications.