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Taiwan
الشخص الذي يمكن الاتصال به Mr. Evan
6F, No. 168, Lian Cheng Rd.,, Chung Ho, Taipei
DDR3 Module: * VDDQ = 1.5V (+/-) 0.**5V * 8 independent internal bank * Programmable /CAS Latency : (4), 5, 6, 7, 8, 9, *0, (*1 for high density only) * Programmable /CAS Write Latency (CWL) = 5 (DDR****0), 6 (DDR*****6), 7 (DDR*****3), 8 (DDR*****0) , 9(DDR*****0) * *-bit pre-fetch * Bi-directional Differential Data-Strobe * Internal(self) calibration * On Die Termination using ODT pin * Average Refresh Period 7.8us at lower than TCASE *5¢XC, 3.9us at *5¢XC < TCASE ? *5¢XC * All of Lead-free products are compliant for RoHS
