Description

1.0 EZ-USB FX2 Features

• Single-chip integrated USB 2.0 Transceiver, SIE, and

Enhanced ***1 Microprocessor

• Software: ***1 code runs from:

—Internal RAM, which is downloaded via USB

—Internal RAM, which is loaded from EEPROM

—External memory device (**8 pin package

• Four programmable BULK/INTERRUPT/

ISOCHRONOUS endpoints

—Buffering options: double, triple and quad

• *- or **-bit external data interface

•GPIF

—Allows direct connection to most parallel interface

—Programmable waveform descriptors and configu-

ration registers to define waveforms

—Supports multiple Ready (RDY) inputs and Control

(CTL) outputs

• Integrated, industry standard enhanced ***1:

—Up to **-MHz clock rate

—Four clocks per instruction cycle

—Two USARTS

—Three counter/timers 

—Expanded interrupt system

—Two data pointers

• Supports bus-powered applications by using renumer-

ation

• 3.3V operation

• Smart Serial Interface Engine

• Vectored USB interrupts

• Separate data buffers for the SETUP and DATA portions

of a CONTROL transfer

• Integrated I

2C-compatible controller, runs at **0 or **0

kHz

• **-MHz, **-MHz, or **-MHz ***1 operation

• Four integrated FIFOs

—Brings glue and FIFOs inside for lower system cost

—Automatic conversion to and from **-bit buses

—Master or slave operation

—FIFOs can use externally supplied clock or asyn-

chronous strobes

—Easy interface to ASIC and DSP ICs

• Special autovectors for FIFO and GPIF interrupts

• Up to *0 general-purpose I/Os

• Four package options—***-pin TQFP, ***-pin TQFP,

**-pin QFN and **-pin SSOP

• Four packages are defined for the family: *6 SSOP, *6

QFN, **0 TQFP, and **8 TQFP